The memory cells of dynamic random access memories (DRAMs) which are arranged in an array having a configuration of intersecting wordlines and digit lines are comprised of two main components, a field-effect transistor (FET) and a capacitor. In DRAM cells utilizing a conventional planar capacitor, far more chip surface area is dedicated to the planar capacitor than to the field-effect transistor. In a typical construction the wordlines are generally etched from a polysilicon-1 layer. A doped region of monocrystalline silicon substrate functions as the lower capacitor plate (storage node), while a polysilicon-2 generally functions as the upper capacitor plate (cell plate).
Although planar capacitors have generally proven adequate for use in DRAM chips up to the 1-megabit level, they are considered to be unusable for more advanced DRAM generations. As component density in memory chips has increased, the shrinkage of cell capacitor size has resulted in a number of problems. Firstly, the alpha-particle component of normal background radiation can generate hole-electron pairs in the silicon substrate, which functions as the lower capacitor plate. This phenomena will cause a charge stored within the affected cell capacitor to rapidly dissipate, resulting in a "soft" error. Secondly, the sense amplifier differential signal is reduced. This aggravates noise sensitivity and makes it more difficult to design a sense amplifier having appropriate signal selectivity. Thirdly, as cell capacitor size is decreased, the cell refresh time must generally be shortened, thus requiring more frequent interruptions for refresh overhead. The difficult goal of a DRAM designer is to increase or, at least, maintain cell capacitance as cell size shrinks, without resorting to processes that reduce product yield or that markedly increase the number of masking and deposition steps in the production process.
Some manufactures of 4-megabit DRAMs are utilizing cell designs based on nonplanar capacitors. Two basic nonplanar capacitor designs are currently in use: the trench capacitor and the stacked capacitor. Both types of nonplanar capacitors typically require a greater number of masking, deposition and etching steps for their manufacture than does a planar capacitor.
In a trench capacitor, charge is stored primarily vertically, as opposed to horizontally as in the planar capacitor. Since trench capacitors are fabricated in trenches which are etched in the substrate, the typical trench capacitor, like the planar capacitor, is subject to soft errors. In addition, there are several other problems inherent in the trench design. One problem is that of trench-to-trench charge leakage, caused by the parasitic transistor effect between adjacent trenches. Another problem is the difficulty of completely cleaning the trenches during the fabrication process; failure to completely clean a trench will generally result in a defective cell.
The stacked capacitor design, on the other hand, has proven somewhat more reliable and easier to fabricate than the trench design. Since both the lower and the upper plates of a typical stacked capacitor are formed from individual polysilicon layers, the stacked capacitor is generally much less susceptible to soft errors than either the planar or trench capacitors. By placing both the wordline and the digit line beneath the capacitive layers, and having the lower layer make contact with the substrate by means of a buried contact, some manufacturers have created stacked capacitor designs in which vertical portions of the capacitor contribute significantly to the total charge storing capacity. Since a stacked capacitor generally covers not only the entire area of a cell (including the cell's access FET), but adjacent field oxide regions as well, capacitance is considerably enhanced over that available from a planar type cell.
The method for forming the typical fin configuration stacked capacitor uses polycrystalline silicon/nitride layers to implement spacing of the fins. The method is complicated and employs multi-depositions and subsequent etch steps to create this stacked capacitor fin structure.
Alternatives for increasing capacitance comprise utilizing materials having larger dielectric constants, decreasing the thickness of the dielectric (decreasing the distance between the capacitor plates), or increasing capacitor surface area by texturizing the polycrystalline silicon surface.
One experimental method for increasing the capacitor surface area is the fabrication of a storage node capacitor having a double-wall crown shaped lower capacitor plate structure wherein the fabrication of the structure is initiated by etching an opening in an SiO.sub.2 interlayer in order to expose a contact area of the substrate. A first polycrystalline silicon layer is then deposited to overlie the surface of the SiO.sub.2 interlayer and the substrate contact area. Next SiO.sub.2 is deposited in conjunction with a spacer etch to form vertical portions of SiO.sub.2 adjacent to the polycrystalline silicon and forming sidewalls of the opening. A second polycrystalline silicon layer is then deposited overlying the portions of SiO.sub.2 and overlying the first polycrystalline silicon layer still exposed after the SiO.sub.2 deposition. The second polycrystalline silicon layer directly contacts the first polycrystalline silicon layer overlying the contact area of the substrate. The remaining portion of the opening is filled with SiO.sub.2. The first and second polycrystalline silicon layers are etched to expose the SiO.sub.2. Next the SiO.sub.2 is etched completing the fabrication of the lower capacitor plate structure which comprises the first and second polycrystalline silicon layers remaining after the etches. Thus the lower capacitor plate comprises a two layer lower portion of polycrystalline silicon in contact with the substrate and comprises two annular rings extending vertically from the two layer portion in contact with the substrate.